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VNH2SP30-E
AUTOMOTIVE FULLY INTEGRATED H-BRIDGE MOTOR DRIVER
Table 1. General Features
Type VNH2SP30-E RDS(on) 19 m max (per leg)
Figure 1. Package
Iout
30 A Vccmax 41 V
s s
OUTPUT CURRENT: 30A
5V LOGIC LEVEL COMPATIBLE INPUTS s UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN s OVERVOLTAGE CLAMP s THERMAL SHUT DOWN s CROSS-CONDUCTION PROTECTION s LINEAR CURRENT LIMITER s VERY LOW STAND-BY POWER CONSUMPTION s PWM OPERATION UP TO 20 KHz s PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF VCC s CURRENT SENSE OUTPUT PROPORTIONAL TO MOTOR CURRENT s IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE DESCRIPTION The VNH2SP30-E is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic High-Side drivers and two Low-Side switches. The High-Side driver switch is designed using STMicroelectronic's well known and proven proprietary VIPowerTM M0 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/ protection circuitry. Table 2. Order Codes
Package Tube
VNH2SP30-E
MultiPowerSO-30
The Low-Side switches are vertical MOSFETs manufactured using STMicroelectronic's proprietary EHD (`STripFETTM') process.The three dice are assembled in MultiPowerSO-30 package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals IN A and IN B can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAG A/ENA or DIAGB/ EN B, when connected to an external pull-up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in the truth table on page 14. The CS pin allows to monitor the motor current by delivering a current proportional to its value. The PWM, up to 20KHz, lets us to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin will turn off both the LSA and LSB switches. When PWM rises to a high level, LSA or LSB turn on again depending on the input pin state.
Tape and Reel
VNH2SP30TR-E
MultiPowerSO-30
Rev. 1 September 2004 1/26
VNH2SP30-E
Figure 2. Block Diagram
VCC
OVERTEMPERATURE A
OV + UV
OVERTEMPERATURE B
CLAMP HSA
CLAMP HSB
HSA
DRIVER HSA
LOGIC
DRIVER HB S
HSB
CURRENT LIMITATION A OUTA CLAMP LSA
DRIVER LSA
CURRENT LIMITATION B
1/K
1/K CLAMP LSB
DRIVER LS B
OUTB
LSA
LSB
GNDA
DIAGA/ENA INA
CS
PWM INB DIAGB/ENB
GNDB
Figure 3. Configuration Diagram (Top View)
OUTA Nc VCC Nc INA ENA/DIAGA Nc PWM CS ENB/DIAGB INB Nc VCC Nc OUTB
1
30
OUTA Heat Slug3
OUTA Nc GNDA GNDA GNDA OUTA Nc VCC Nc OUTB
VCC Heat Slug1
OUTB
Heat Slug2
GNDB GNDB GNDB
16
15
Nc OUTB
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VNH2SP30-E
Table 3. Pin Definitions And Functions
Pin No 1, 25, 30 2,4,7,12,14,17, 22, 24,29 3, 13, 23 6 5 8 9 11 10 15, 16, 21 26, 27, 28 18, 19, 20 Symbol OUTA, Heat Slug2 NC VCC, Heat Slug1 ENA/DIAGA INA PWM CS INB ENB/DIAGB OUTB, Heat Slug3 GNDA GNDB Function Source of High-Side Switch A / Drain of Low-Side Switch A Not connected Drain of High-Side Switches and Power Supply Voltage Status of High-Side and Low-Side Switches A; Open Drain Output Clockwise Input PWM Input Output of Current sense Counter Clockwise Input Status of High-Side and Low-Side Switches B; Open Drain Output Source of High-Side Switch B / Drain of Low-Side Switch B Source of Low-Side Switch A (*) Source of Low-Side Switch B (*)
Note: (*) GNDA and GNDB must be externally connected together
Table 4. Pin Functions Description
Name VCC GNDA GNDB OUTA OUTB INA INB PWM ENA/DIAGA ENB/DIAGB CS Description Battery connection. Power grounds, must always be externally connected together. Power connections to the motor. Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and counterclockwise). Voltage controlled input pin with hysteresis, CMOS compatible.Gates of Low-Side FETS get modulated by the PWM signal during their ON phase allowing speed control of the motor Open drain bidirectional logic pins.These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low by the device (see truth table in fault condition). Analog current sense output. This output sources a current proportional to the motor current. The information can be read back as an analog voltage across an external resistor.
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VNH2SP30-E
Table 5. Block Descriptions (see Block Diagram)
Name LOGIC CONTROL OVERVOLTAGE + UNDERVOLTAGE HIGH SIDE AND LOW SIDE CLAMP VOLTAGE HIGH SIDE AND LOW SIDE DRIVER LINEAR CURRENT LIMITER OVERTEMPERATURE PROTECTION FAULT DETECTION Description Allows the turn-on and the turn-off of the High Side and the Low Side switches according to the truth table. Shut-down the device outside the range [5.5V..16V] for the battery voltage. Protect the High Side and the Low Side switches from the high voltage on the battery line in all configuration for the motor. Drive the gate of the concerned switch to allow a proper RDS(on) for the leg of the bridge. Limits the motor current, by reducing the High Side Switch gate-source voltage when short-circuit to ground occurs. In case of short-circuit with the increase of the junction's temperature, shuts-down the concerned High Side to prevent its degradation and to protect the die. Signalize an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin.
Table 6. Absolute Maximum Rating
Symbol VCC Imax IR IIN IEN Ipw VCS Parameter Supply Voltage Maximum Output Current (continuous) Reverse Output Current (continuous) Input Current (INA and INB pins) Enable Input Current (DIAGA/ENA and DIAGB/ENB pins) PWM Input Current Current Sense Maximum Voltage Electrostatic Discharge (R=1.5k, C=100pF) - CS pin - logic pins - output pins: OUTA, OUTB, VCC Junction Operating Temperature Case Operating Temperature Storage Temperature Value + 41 30 -30 +/- 10 +/- 10 +/- 10 -3/+15 2 4 5 Internally Limited -40 to 150 -55 to 150 Unit V A A mA mA mA V kV kV kV C C C
VESD
Tj Tc TSTG
Figure 4. Current and Voltage Conventions
IS VCC IINA IINB IENA IENB VINA VINB VENA VENB Vpw IGND INA IN B DIAGA/ENA DIAGB/ENB PWM Ipw VCC OUTA OUTB CS ISENSE VSENSE GND A GNDB GND VOUTB IOUTA IOUTB VOUTA
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VNH2SP30-E
Table 7. Thermal Data See MultiPowerSO-30 Thermal Data section (page ) ELECTRICAL CHARACTERISTICS (VCC=9V up to 16V; -40CSymbol VCC Parameter Operating supply voltage Off state: INA=INB=PWM=0; Tj=25C; Test Conditions Min. 5.5 Typ. Max. 16 Unit V
VCC=13V
IS Supply Current INA=INB=PWM=0 On state: INA or INB=5V, no PWM RONHS RONLS Vf Static High-Side resistance Static Low-Side resistance High Side Free-wheeling Diode Forward Voltage High Side Off State Output Current (per channel) Dynamic IRM Cross-conduction Current IOUT=15A (see fig. 8) IOUT=15A; Tj=25C IOUT=15A; Tj= - 40 to 150C IOUT=15A; Tj=25C IOUT=15A; Tj= - 40 to 150C If=15A Tj=25C; VOUTX=ENX=0V; VCC=13V Tj=125C; VOUTX=ENX=0V; VCC=13V
12
30 60 10 14 28 5 10
A A mA m m m m V A A
0.8
1.1 3 5
IL(off)
0.7
A
Table 9. Logic Inputs (INA, INB, ENA, ENB)
Symbol VIL VIH VIHYST VICL IINL IINH VDIAG Parameter Input Low Level Voltage Input High Level Voltage Input Hysteresis Voltage Input Clamp Voltage Input Current Input Current Enable Output Low Level Voltage Test Conditions Normal operation (DIAGX/ENX pin acts as an input pin) Normal operation (DIAGX/ENX pin acts as an input pin) Normal operation (DIAGX/ENX pin acts as an input pin) IIN=1mA IIN=-1mA VIN=1.25 V VIN=3.25 V Fault operation (DIAGX/ENX pin acts as an output pin); IEN=1mA 3.25 0.5 5.5 -1.0 1 10 0.4 6.3 -0.7 7.5 -0.3 Min. Typ. Max. 1.25 Unit V V V V V A A V
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VNH2SP30-E
ELECTRICAL CHARACTERISTICS (continued) Table 10. PWM
Symbol Vpwl Ipwl Vpwh Ipwh Vpwhhyst
Vpwcl CINPWM PWM PWM PWM PWM PWM
Parameter Low Level Voltage Pin Current High Level Voltage Pin Current Hysteresis Voltage
Test Conditions
Vpw=1.25V Vpw=3.25V Ipw = 1 mA Ipw = -1 mA VIN =2.5V
Min
1 3.25
Typ
Max 1.25
10 0.5 VCC+0.3 -6.0 VCC+0.7 VCC+1.0 -4.5 -3.0 25
PWM Clamp Voltage PWM Pin Input Capacitance
Unit V A V A V V
V pF
Table 11. Switching (VCC=13V, RLOAD=0.87)
Symbol f td(on) td(off) tr tf Parameter PWM Frequency Turn-on Delay Time Turn-off Delay Time Rise Time Fall Time Delay Time During Change of Operating Mode High Side Free Wheeling Diode Reverse Recovery Time PWM Minimum off time Test Conditions Input rise time < 1s (see fig. 8) Input rise time < 1s (see fig. 8) (see fig. 7) (see fig. 7) (see fig. 6) (see fig. 9) 9V1 1.2
600 110
tDEL
trr
-40CIOUT =15A
6
s
Table 12. Protection And Diagnostic
Symbol VUSD VOV ILIM VCLP TTSD TTR THYST Parameter Undervoltage Shut-down Undervoltage Reset Overvoltage Shut-down High-Side Current Limitation Total Clamp Voltage (VCC to GND) Thermal Shut-down Temperature Thermal Reset Temperature Thermal Hysteresis Test Conditions Min Typ 4.7 19 50 48 175 Max 5.5 22 70 54 200 Unit V V V A V C C C
16 30 IOUT=15A VIN = 3.25 V 43 150 135 7
15
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VNH2SP30-E
ELECTRICAL CHARACTERISTICS (continued) Table 13. Current Sense (9VSymbol K1 K2 Parameter IOUT/ISENSE IOUT/ISENSE Test Conditions IOUT =30A; RSENSE=1.5k Tj= - 40 to 150C IOUT =8A; RSENSE=1.5k Tj= - 40 to 150C IOUT =30A; RSENSE=1.5k Tj= - 40 to 150C IOUT >8A; RSENSE=1.5k Tj= - 40 to 150C IOUT =0A; VSENSE=0V; Tj= - 40 to 150C Min 9665 9096 -8 -10 0 Typ 11370 11370 Max 13075 13644 +8 +10 65 % % A Unit
dK1 / K1 (*) Analog sense current drift dK2 / K2 (*) Analog sense current drift ISENSEO Analog Sense Leakage Current
Note:(*) Analog sense current drift is deviation of factor K for a given device over (-40C to 150C and 9VWAVEFORMS AND TRUTH TABLE Table 14. Truth Table In Normal Operating Conditions
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. PWM pin usage: in all cases, a "0" on the PWM pin will turn-off both LSA and LSB switches. When PWM rises back to "1", LSA or LSB turn on again depending on the input pin state. OUTB H L H L CS High Imp. ISENSE=I OUT/K
ISENSE=I OUT/K
INA 1 1 0 0
INB 1 0 1 0
DIAGA/ENA 1 1 1 1
DIAGB/ENB 1 1 1 1
OUTA H H L L
Operating mode Brake to VCC Clockwise (CW) Counterclockwise
(CCW)
High Imp.
Brake to GND
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VNH2SP30-E
Figure 5. Typical Application Circuit For Dc To 20khz PWM OperationShort Circuit Protection
VCC
Reg 5V + 5V 3.3K 1K DIAGA/ENA 1K
+5V
VCC
DIAGB/ENB
3.3K
1K
HSA
OUTA
HSB
OUTB
C
1K 10K
PWM
INA
INB
LSA
CS
LSB
1K
M
GNDA
S 100K G D b) N MOSFET
> 50uF
33nF
1.5K
GNDB
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device. The fault conditions are: - overtemperature on one or both high sides (for example if a short to ground occurs as it could be the case described in line 1 and 2 in the table below); - short to battery condition on the output (saturation detection on the Low-Side Power MOSFET). Possible origins of fault conditions may be: OUTA is shorted to ground ---> overtemperature detection on high side A. OUTA is shorted to VCC ---> Low-Side Power MOSFET saturation detection. When a fault condition is detected, the user can know
which power element is in fault by monitoring the IN A, INB, DIAGA/ENA and DIAGB/ENB pins. In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the respective output (OUTX) again, the input signal must rise from low to high level.
Table 15. Truth Table In Fault Conditions (Detected On OUTA)
INA 1 1 0 0 X X X INB 1 0 1 0 X 1 0 DIAGA/ENA 0 0 0 0 0 0 0 DIAGB/ENB 1 1 1 1 0 1 1 OUTA OPEN OPEN OPEN OPEN OPEN OPEN OPEN OUTB H L H L OPEN H L CS High Imp. High Imp. IOUTB/K High Imp. High Imp. IOUTB/K High Imp.
Fault Information
Protection Action
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VNH2SP30-E
Table 16. Electrical Transient Requirements
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 Class C E Test Level I -25V +25V -25V +25V -4V +26.5V Test Level II -50V +50V -50V +50V -5V +46.5V Test Level III -75V +75V -100V +75V -6V +66.5V Test Level IV -100V +100V -150V +100V -7V +86.5V Test Levels Result III C C C C C E Test Levels Delays and Impedance 2ms, 10 0.2ms, 10 0.1s, 50 0.1s, 50 100ms, 0.01 400ms, 2 Test Levels Result IV C C C C C E
Test Levels Result I C C C C C C
Test Levels Result II C C C C C E
Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
Reverse Battery Protection Three possible solutions can be thought of: a) a Schottky diode D connected to V CC pin b) a N-channel MOSFET connected to the GND pin (see Typical Application Circuit on page 8) c) a P-channel MOSFET connected to the VCC pin
The device sustains no more than -30A in reverse battery conditions because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNH2SP30-E will be pulled down to the VCC line (approximately -1.5V). Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum target reverse current through C I/Os, series resistor is: V -V IOs CC R = --------------------------------I Rmax
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VNH2SP30-E
Figure 6. Definition Of The Delay Times Measurement
VINA,
t
VINB
t
PWM
t
ILOAD tDEL
tDEL
t
Figure 7. Definition Of The Low Side Switching Times
PWM
t
VOUTA, B 90% 80%
tf
20%
10%
tr
t
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VNH2SP30-E
Figure 8. Definition Of The High Side Switching Times
VINA,
tD(on)
tD(off)
t
VOUTA
90%
10%
t
Figure 9. Definition Of Dynamic Cross Conduction Current During A Pwm Operation
IN A=1, IN B=0
PWM
t
IMOTOR
t
VOUTB
t
ICC IRM
t
trr
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VNH2SP30-E
Figure 10. Waveforms in full bridge operation
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS (*)
tDEL (*) CS BEHAVIOUR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE
tDEL
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA INB ILIM IOUTA->OUTB TTSD TTR
Tj
DIAGA/ENA DIAGB/ENB CS normal operation
Tj > TTR
OUTA shorted to ground
normal operation
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VNH2SP30-E
Figure 11. Waveforms In Full Bridge Operation (continued)
OUTA shorted to VCC and undervoltage shutdown
INA INB OUTA OUTB IOUTA->OUTB DIAGB/ENB DIAGA/ENA CS Vundefined undefined
normal operation
OUTA shorted to VCC
normal operation
undervoltage shutdown
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VNH2SP30-E
Figure 12. Half-bridge Configuration The VNH2SP30-E can be used as a high power half-bridge driver achieving an On resistance per leg of 9.5m. Suggested configuration is the following:
VCC
INA INB DIAGA/ENA DIAGB/ENB PWM OUTA OUTB
INA INB DIAGA/ENA DIAGB/ENB PWM
M
OUTA
OUTB
GNDA
GNDB
GNDA
GNDB
Figure 13. Multi-motors Configuration The VNH2SP30-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAG X/EN X pins allow to put unused half-bridges in high impedance. Suggested configuration is the following:
VCC
INA INB DIAGA/ENA DIAGB/ENB PWM OUTA OUTB
INA INB DIAGA/ENA DIAGB/ENB PWM
M2
OUTA
OUTB
GNDA
GNDB
GNDA
GNDB
M1
M3
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VNH2SP30-E
Figure 14. On State Supply Current
Is (mA)
6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 10 5 0 -50 -25 0 25 50 75 100 125 150 175 35 30 25 20 15
Figure 17. Off State Supply Current
Is (A)
50 45
Vcc=13V INA or INB=5V
Vcc=13V
40
Tc (C)
Tc (C)
Figure 15. High Level Input Current
Iinh (A)
5 4.5
Figure 18. Input Clamp Voltage
Vicl (V)
8 7.75
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
7.5 7.25 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 -50
Iin =1mA
-25
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
Figure 16. Input High Level Voltage
Vih (V)
3 2.9 2.8
Figure 19. Input Low Level Voltage
Vil (V)
3 2.75 2.5
2.7 2.6 2.5 2.4 2.3 1.5 2.2 2.1 2 -50 -25 0 25 50 75 100 125 150 175 1.25 1 -50 -25 0 25 50 75 100 125 150 175 2.25 2 1.75
Tc (C)
Tc (C)
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VNH2SP30-E
Figure 20. Input Hysteresis Voltage
Vihyst (V)
2 1.75
Figure 23. High Level Enable Pin Current
Ienh (A)
8 7
Vcc=13V
1.5 1.25 1 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 175 6 5 4 3 2 1 0 -50
Ven=3.25V
-25
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
Figure 21. Delay Time during change of operation mode
tdel (s)
1000 900
Figure 24. Enable Clamp Voltage
Vencl (V)
-0.2 -0.3
800 700 600 500 400 -0.7 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175 -0.8 -0.9 -1 -50 -0.4 -0.5 -0.6
Ien=-1mA
-25
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
Figure 22. High Level Enable Voltage
Venh (V)
3.6 3.4
Figure 25. Low Level Enable Voltage
Venl (V)
3 2.8
Vcc=9V
3.2 3 2.8 2.6 2.4 2.2 2 1.8 1.6 -50 -25 0 25 50 75 100 125 150 175 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 -50 -25
Vcc=9V
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
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VNH2SP30-E
Figure 26. PWM High Level Voltage
Vpwh (V)
5 4.5
Figure 29. PWM Low Level Voltage
Vpwl (V)
2.6 2.4
Vcc=9V
4 3.5 3 2.5 2 1.5
Vcc=9V
2.2 2 1.8 1.6 1.4
1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 1.2 1 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 27. PWM High Level Current
Ipwh (A)
8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Figure 30. Overvoltage Shutdown
Vov (V)
30 27.5 25 22.5 20 17.5 15 12.5 10 -50 -25 0 25 50 75 100 125 150 175
Vcc=9V Vpw=3.25V
Tc (C)
Tc (C)
Figure 28. Undervoltage Shutdown
Vusd(V)
8 7 6
Figure 31. Current Limitation
Ilim (A)
80 75 70 65
5 4 3 2
60 55 50 45 40
1 0 -50 -25 0 25 50 75 100 125 150 175
35 30 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VNH2SP30-E
Figure 32. On State High Side Resistance Vs. Tcase
Ronhs (mOhm)
40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 35. On State Low Side Resistance Vs. Tcase
Ronls (mOhm)
40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 150 175
Vcc=9V; 16V Iout=15A
Iload=12A Vcc=9V; 13V; 18V
Tc (C)
Tc (C)
Figure 33. Turn-on Delay Time
td(on) (s)
260 240 220 200 180 160 140 120 100 80 60 -50 -25 0 25 50 75 100 125 150 175
Figure 36. Turn-off Delay Time
td(off) (s)
200 190 180 170 160 150 140 130 120 110 100 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 34. Output Voltage Rise Time
tr (s)
2 1.8 1.6
Figure 37. Output Voltage Fall Time
tf (s)
8 7 6
1.4
5
1.2
4
1 0.8 0.6 0.4 0.2 -50 -25 0 25 50 75 100 125 150 175
3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VNH2SP30-E
MultiPowerSO-30TM Thermal Data Figure 38. MultiPowerSO-30TM PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 16cm2).
Figure 39. Chipset Configuration
HIGH SIDE CHIP HSAB
LOW SIDE CHIP A LSA
LOW SIDE CHIP B LSB
Figure 40. Auto and mutual Rthj-amb Vs PCB copper area in open box free air condition (according to page 20 definitions)
45 40 35 30 25 20 15 C/W 10 5 0 0 5 10 15 cm2 of Cu Area (refer to PCB layout) 20
RthHS RthLS RthHSLS RthLSLS
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VNH2SP30-E
Table 17. Thermal Calculation In Clockwise And Anti-clockwise Operation In Steady-state Mode
HSA ON OFF HSB OFF ON LSA OFF ON LSB ON OFF TjHSAB PdHSA x RthHS + PdLSB x RthHSLS + Tamb PdHSB x RthHS + PdLSA x RthHSLS + Tamb TjLSA PdHSA x RthHSLS + PdLSB x RthLSLS + Tamb PdHSB x RthHSLS + PdLSA x RthLS + Tamb TjLSB PdHSA x RthHSLS + PdLSB x RthLS + Tamb PdHSB x RthHSLS + PdLSA x RthLSLS + Tamb
Thermal
Resistances
Definition
(values
Single Pulse Thermal Impedance Definition (values according to the PCB heatsink area) ZthHS = High Side Chip Thermal Impedance Junction to Ambient ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient between High Side and Low Side Chips ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side Chips
according to the PCB heatsink area) RthHS = RthHSA = RthHSB = High Side Chip Thermal Resistance Junction to Ambient (HS A or HSB in ON state) RthLS = R thLSA = R thLSB = Low Side Chip Thermal Resistance Junction to Ambient RthHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient between High Side and Low Side Chips RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side Chips
Thermal Calculation In Transient Mode (*) TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + T amb TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS x PdLSB + T amb
Pulse Calculation Formula
Z TH
=
R TH + Z THtp ( 1 - ) = tp T
where
(*) Calculation is valid in any dynamic operating condition. Pd values set by user.
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VNH2SP30-E
Figure 41. MultiPowerSO-30 HSD Thermal Impedance Junction Ambient Single Pulse
100
Footprint 4 cm2 8 cm2 ZthHS
10
16 cm2 Footprint 4 cm2 8 cm2
ZthHSLS
C/W
16 cm2
1
0 .1 0 .0 0 1
0 .0 1
0 .1
ti m e ( se c )
1
10
10 0
100 0
Figure 42. MultiPowerSo-30 LSD Thermal Impedance Junction Ambient Single Pulse
100
ZthLS
Footprint 4 cm2 8 cm2 16 cm2 Footprint 4 cm2 8 cm2 16 cm2
10
ZthLSLS
C/W
1
0 .1 0 .0 0 1
0 .0 1
0 .1
t i m e ( se c )
1
10
100
1000
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Figure 43. Thermal fitting model of an H-Bridge in MultiPowerSO-30
Table 18. Thermal Parameter (*)
Area/island (cm2) R1=R7 (C/W) R2=R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) R9=R15 (C/W) R10=R16 (C/W) R11=R17 (C/W) R12=R18 (C/W) R13=R19 (C/W) R14=R20 (C/W) R21=R22=R23 (C/W) C1=C7 (W.s/C) C2=C8 (W.s/C) C3=C11=C17 (W.s/C) C4=C13=C19 (W.s/C) C5 (W.s/C) C6 (W.s/C) C9=C15 (W.s/C) C10=C16 (W.s/C) C12=C18 (W.s/C) C14=C20 (W.s/C) Footprint 0.05 0.3 0.5 1.3 1.4 44.7 0.2 0.4 0.8 1.5 20 46.9 115 0.005 0.008 0.01 0.3 0.6 5 0.003 0.006 0.075 2.5 4 8 16
39.1
31.6
23.7
36.1
30.4
20.8
7
9
11
3.5
4.5
5.5
Note: (*) The blank space means that the value is the same as the previous one.
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PACKAGE MECHANICAL Table 19. MultiPowerSO-30 Mechanical Data
Symbol A A2 A3 B C D E E1 e F1 F2 F3 L N S 0deg 5.55 4.6 9.6 0.8 1.85 0 0.42 0.23 17.1 18.85 15.9 16 1 6.05 5.1 10.1 1.15 10deg 7deg 17.2 millimeters Min. Typ Max. 2.35 2.25 0.1 0.58 0.32 17.3 19.15 16.1
Figure 44. MultiPowerSO-30 Package Dimensions
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Figure 45. MultiPowerSO-30 Suggested Pad Layout
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REVISION HISTORY
Date Revision Sep. 2004 1 - First issue. Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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